From 23d3840c98f94e42e18ee609bd74bfb48458b1ed Mon Sep 17 00:00:00 2001 From: Wenhui Fan Date: Tue, 28 Oct 2025 14:11:03 +0800 Subject: [PATCH] EDAC/amd64: The width of hash value is 2 bits for Hygon family 18h model 6h processors commit 95e0df888d5d977c100b27b627b800a2a09baba8 anolis. ANBZ: #26500 It has 2 bits hash value when hash enabled for hygon family 18h model 6h. Hygon-SIG: commit none hygon anolis: EDAC/amd64: The width of hash value is 2 bits for Hygon family 18h model 6h processors Hygon-SIG: commit 95e0df888d5d anolis EDAC/amd64: The width of hash value is 2 bits for Hygon family 18h model 6h processors Backport to change EDAC hash value bits for Hygon Processors. Signed-off-by: Wenhui Fan Cc: hygon-arch@list.openanolis.cn Reviewed-by: Guixin Liu Link: https://gitee.com/anolis/cloud-kernel/pulls/5912 [ Aichun Shi: amend commit log ] Signed-off-by: Aichun Shi --- drivers/edac/amd64_edac.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f70f448d6f84..d2cade3a2eee 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1444,7 +1444,11 @@ static int hygon_umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, case 5: intlv_num_chan = 3; break; case 7: intlv_num_chan = 4; break; - case 8: intlv_num_chan = 1; + case 8: + if (boot_cpu_data.x86_model >= 0x6) + intlv_num_chan = 2; + else + intlv_num_chan = 1; hash_enabled = true; break; default: @@ -1588,10 +1592,16 @@ static int hygon_umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, (ctx.ret_addr >> 30) ^ cs_id; - hashed_bit &= BIT(0); - - if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(intlv_addr_bit); + if (boot_cpu_data.x86_model >= 0x6) { + hashed_bit &= 0x3; + if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & 0x3)) + ctx.ret_addr = (ctx.ret_addr & ~((u64)3 << intlv_addr_bit)) | + (hashed_bit << intlv_addr_bit); + } else { + hashed_bit &= BIT(0); + if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0))) + ctx.ret_addr ^= BIT(intlv_addr_bit); + } } /* The channel hashing process. */ -- Gitee