diff --git a/sig/RISCV_SIG/assets/add_cmdline.png b/sig/RISCV_SIG/assets/add_cmdline.png new file mode 100644 index 0000000000000000000000000000000000000000..6456191fa9730596f59ae9f750f26649a9f7b911 Binary files /dev/null and b/sig/RISCV_SIG/assets/add_cmdline.png differ diff --git a/sig/RISCV_SIG/assets/boot_grub.png b/sig/RISCV_SIG/assets/boot_grub.png new file mode 100644 index 0000000000000000000000000000000000000000..b2980dfca012f0f2892a53e1c1406a5a378a64b6 Binary files /dev/null and b/sig/RISCV_SIG/assets/boot_grub.png differ diff --git a/sig/RISCV_SIG/assets/select_kernel.png b/sig/RISCV_SIG/assets/select_kernel.png new file mode 100644 index 0000000000000000000000000000000000000000..fdc40c3e54dd5d83211b7711411e011029d60522 Binary files /dev/null and b/sig/RISCV_SIG/assets/select_kernel.png differ diff --git "a/sig/RISCV_SIG/content/RVA23 \351\225\234\345\203\217 QEMU \345\220\257\345\212\250.md" "b/sig/RISCV_SIG/content/RVA23 \351\225\234\345\203\217 QEMU \345\220\257\345\212\250.md" new file mode 100644 index 0000000000000000000000000000000000000000..2a8694bfe819b195aa3de46e4de9c3d9e80d77c8 --- /dev/null +++ "b/sig/RISCV_SIG/content/RVA23 \351\225\234\345\203\217 QEMU \345\220\257\345\212\250.md" @@ -0,0 +1,40 @@ + +# 镜像地址 +https://build.openanolis.cn/kojifiles/rsync/alt/anolis/23/images/AnolisOS-23.3-rva23-riscv64.qcow2 +# QEMU 环境 +参考 [QEMU 启动环境](https://openanolis.cn/sig/RISCV/doc/1395406941639639076) + +# 启动脚本 +参考 +```shell + qemu-system-riscv64 -d int -D interrupt_log.txt \ + -M virt,pflash0=pflash0,pflash1=pflash1,acpi=on,aia=aplic-imsic \ + -cpu rva23s64 \ + -m 64G -smp 64 \ + -device virtio-gpu-pci -full-screen \ + -device qemu-xhci \ + -device usb-kbd \ + -device virtio-rng-pci \ + -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ + -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ + -bios fw_dynamic.bin \ + -device virtio-net-device,netdev=net0 \ + -netdev user,id=net0,hostfwd=tcp::2230-:22 \ + -device virtio-blk-pci,drive=hd0 \ + -drive file=AnolisOS-23.3-rva23-riscv64.qcow2,if=none,id=hd0,format=qcow2 \ + -nographic +``` + +# 启动步骤 +1. 手动启动 grub + - qemu 启动后自动进入 grub shell, + - 输入 fs0: 进入目录 + - 输入 cd EFI/anolis + - 输入 grubriscv64.efi 进入 grub 启动流程 + ![alt text](../assets/boot_grub.png) +2. 修改 kernel cmdline + - 在 grub 选择页面中，选中 6.6.102-5.1 内核，按 e 进入编辑页面 + ![alt text](../assets/select_kernel.png) + - 在 linux 开头的这行添加 `per_numa_node_futex=disable` + ![alt text](../assets/add_cmdline.png) + - ctrl + x 保存配置并启动，等待OS启动完成 \ No newline at end of file diff --git "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" index c5fda9f15343994f39ed9803b579f7ebe265ecf7..cd9bfc47324476cc0305ded1f9412c9fc6315331 100644 --- "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" +++ "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/ISA extension.md" @@ -75,17 +75,17 @@ | Svbare | satp 寄存器必须支持 Bare 模式（不进行地址翻译）。| GCC | | | | Sv39 | 虚拟内存系统| 6.6 | 6.6 支持 | | Svade |当页表项的 A/D (Accessed/Dirty) 位为0时进行访问/写入会触发异常。 | [ Add Svade and Svadu Extensions Support](https://lore.kernel.org/all/20240726084931.28924-1-yongxuan.wang@sifive.com/)| https://gitee.com/anolis/cloud-kernel/pulls/5652 | 罗海洋(ZTE)| -| Ssccptr |主存区域支持硬件自动的页表遍历。 | N/A | | | -| Sstvecd |stvec 寄存器支持直接模式。 | NA | | | -| Sstvala | stval 寄存器必须在特定异常时写入错误地址或指令。| NA| | | -| Sscounterenw |scounteren 寄存器中对应性能计数器的位必须是可写的。 | NA | | | +| Ssccptr |主存区域支持硬件自动的页表遍历。 | GCC | | | +| Sstvecd |stvec 寄存器支持直接模式。 | GCC | | | +| Sstvala | stval 寄存器必须在特定异常时写入错误地址或指令。| GCC| | | +| Sscounterenw |scounteren 寄存器中对应性能计数器的位必须是可写的。 | GCC | | | | Svpbmt | 基于页的内存类型，允许为内存页指定不同的缓存策略。| 6.6 支持| | | | Svinval | 提供了SFENCE.INVAL.IR和SINVAL.VMA等指令，允许操作系统以更细的粒度（如单个页表项）来无效化TLB| 6.6 支持| | | Svnapot |支持NAPOT (Naturally Aligned Power-of-Two) 页，优化大内存块的 TLB 映射 | 6.6 支持| | | | Sstc | S 模式时钟中断| 6.6 支持| | | | Sscofpmf |性能计数器的溢出和基于模式的过滤功能。 | 6.6 支持| | | | Ssnpm |指针屏蔽支持。 | [riscv: Userspace pointer masking and tagged address ABI](https://lore.kernel.org/all/20241016202814.4061541-3-samuel.holland@sifive.com/)|https://gitee.com/anolis/cloud-kernel/pulls/5568 | 罗海洋(ZTE)| -| Ssu64xl |sstatus.UXL 必须支持64位用户模式 | NA | | | +| Ssu64xl |sstatus.UXL 必须支持64位用户模式 | GCC | | | | H | | | | | | Ssstateen | | #[target/riscv: add 'sha' support](https://lore.kernel.org/all/20241218114026.1652352-1-dbarboza@ventanamicro.com/) | | | | Shcounterenw | | #[target/riscv: add 'sha' support](https://lore.kernel.org/all/20241218114026.1652352-1-dbarboza@ventanamicro.com/) | | | diff --git "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" index c729bc6074da77d55476f5e076d968e92532eca2..8cdd19ee1d5fa5943901d881cb441f9183f552b6 100644 --- "a/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" +++ "b/sig/RISCV_SIG/content/\345\206\205\346\240\270/RISC-V Server SoC patch \345\233\236\345\220\210\350\267\237\350\270\252.md" @@ -42,26 +42,13 @@ | | [RISC-V: KVM: Allow Svvptc/Zabha/Ziccrse exts for guests](https://lwn.net/Articles/1000289/) | | # ACPI -| Field | Patch List | status | +| Description | upstream | anolis | owner | |-------|-------------|---------| -| Misc. Support | [ACPI: Enable ACPI_PROCESSOR for RISC-V](https://lore.kernel.org/all/20240118062930.245937-4-sunilvl@ventanamicro.com/) | | -| | [riscv: Use the same CPU operations for all CPUs](https://lore.kernel.org/r/20231121234736.3489608-4-samuel.holland@sifive.com) | | -| | [riscv: Deduplicate code in setup_smp()](https://lore.kernel.org/r/20231121234736.3489608-2-samuel.holland@sifive.com) | | -| | [drivers: base: Implement weak arch_unregister_cpu()](https://lore.kernel.org/r/E1r5R3H-00CszC-2n@rmk-PC.armlinux.org.uk) | | -| | [drivers: base: Use present CPUs in GENERIC_CPU_DEVICES](https://lore.kernel.org/r/E1r5R36-00Csz0-Px@rmk-PC.armlinux.org.uk) | | -| | [ACPI: Move ACPI_HOTPLUG_CPU to be disabled on arm64 and riscv](https://lore.kernel.org/r/E1r5R31-00Csyt-Jq@rmk-PC.armlinux.org.uk) | | -| | [arm64: PCI: Migrate ACPI related functions to pci-acpi.c](https://patch.msgid.link/20240812005929.113499-2-sunilvl@ventanamicro.com) | | -| | [RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping](https://lore.kernel.org/r/20231018124007.1306159-2-sunilvl@ventanamicro.com) | | -| RHCT | [clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpu](https://lore.kernel.org/r/20230927170015.295232-5-sunilvl@ventanamicro.com) | | -| | [RISC-V: ACPI: Update the return value of acpi_get_rhct()](https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com) | | -| | [RISC-V: ACPI: RHCT: Add function to get CBO block sizes](https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com) | | -| | [RISC-V: cacheflush: Initialize CBO variables on ACPI systems](https://lore.kernel.org/r/20231018124007.1306159-5-sunilvl@ventanamicro.com) | | -| | [RISC-V: ACPI: RHCT: Add function to get CBO block sizes](https://lore.kernel.org/r/20231018124007.1306159-4-sunilvl@ventanamicro.com) | | -| | [RISC-V: ACPI: Update the return value of acpi_get_rhct()](https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com) | | +| | [RISC-V: ACPI improvements](https://lore.kernel.org/r/20231018124007.1306159-3-sunilvl@ventanamicro.com) | | | PPTT | [riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT](https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com) | | | | [riscv: Prevent a bad reference count on CPU nodes](https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com) | | | | [RISC-V: Select ACPI PPTT drivers](https://lore.kernel.org/r/20240617131425.7526-3-cuiyunhui@bytedance.com) | | -|LPI | [ACPI: RISC-V: Add LPI driver](https://lore.kernel.org/r/20240118062930.245937-3-sunilvl@ventanamicro.com) | | +|LPI | [ACPI: RISC-V: Add LPI driver](https://lore.kernel.org/r/20240118062930.245937-3-sunilvl@ventanamicro.com) | https://gitee.com/anolis/cloud-kernel/pulls/5696| 余方玉（达摩院）| | | [cpuidle: RISC-V: Move few functions to arch/riscv](https://lore.kernel.org/r/20240118062930.245937-2-sunilvl@ventanamicro.com) | | |CPPC | [ACPI: RISC-V: Add CPPC driver](https://lore.kernel.org/r/20240208034414.22579-2-sunilvl@ventanamicro.com) | https://gitee.com/anolis/cloud-kernel/pulls/5538 | | | [RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ](https://lore.kernel.org/r/20240208034414.22579-4-sunilvl@ventanamicro.com) | | @@ -73,7 +60,7 @@ | Field | Description | status | |-------|-------------|---------| | | [RISC-V: ACPI: Add external interrupt controller support](https://lwn.net/Articles/969949/) | | -| | [Linux RISC-V AIA Support](https://lwn.net/Articles/959744/) | | +| | [Linux RISC-V AIA Support](https://lwn.net/Articles/959744/) | https://gitee.com/anolis/cloud-kernel/pulls/5219/commits | https://gitee.com/anolis/cloud-kernel/pulls/5219 | 高睿（ZTE）| | | [RISC-V IPI Improvements](https://lwn.net/Articles/927554/) | | # perf @@ -103,7 +90,7 @@ | | [iommu/riscv: Add irqbypass support](https://lwn.net/Articles/998203/) | | | | [riscv: iommu: Support Svnapot](https://lwn.net/Articles/1013736/) | | | | [RISC-V IOMMU HPM and nested IOMMU support](https://lwn.net/Articles/978457/) | | -| | [Linux RISC-V IOMMU Support](https://lwn.net/Articles/938638/) | | +| | [Linux RISC-V IOMMU Support](https://lwn.net/Articles/938638/) | https://gitee.com/anolis/cloud-kernel/pulls/5473 | 高睿（ZTE）| # Qos | Field | Description | status | @@ -114,7 +101,7 @@ # timer | Field | Description | status | |-------|-------------|---------| -| | [Add Sstc extension support](https://lwn.net/Articles/886863/) | | +| | [Add Sstc extension support](https://lwn.net/Articles/886863/) | 6.6 | # Opt @@ -133,7 +120,7 @@ | | [RISC-V: mm: Make SV48 the default address space](https://lwn.net/Articles/937671/) | | | | [riscv: Memory Hot(Un)Plug support](https://lwn.net/Articles/977258/) | | | | [riscv: Introduce 64K base page](https://lwn.net/Articles/952722/) | | -| | [Add Svade and Svadu Extensions Support](https://lwn.net/Articles/980016/) | | +| | [Add Svade and Svadu Extensions Support](https://lwn.net/Articles/980016/) | https://gitee.com/anolis/cloud-kernel/pulls/5652 | 罗海洋（ZTE）| | | [riscv: Introduce 64K base page](https://lwn.net/Articles/952722/) | | | | [RISC-V: Add dynamic TSO support](https://lwn.net/Articles/961587/) | |