# awesome-AIEDA-works **Repository Path**: oscc-project/awesome-AIEDA-works ## Basic Information - **Project Name**: awesome-AIEDA-works - **Description**: AI4EDA: AI Works for Electronic Design Automation - **Primary Language**: Unknown - **License**: Not specified - **Default Branch**: main - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 0 - **Forks**: 0 - **Created**: 2025-09-03 - **Last Updated**: 2025-09-03 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # AI4EDA: AI Works for Electronic Design Automation We would like to maintain a list of resources that utilize AI to solve problems in Electronic Design Automation ## **AI for Logic Synthesis** ### **AI for Logic Synthesis Dataset and Library** - The mnist database of handwritten digit images for machine learning research - Learning multiple layers of features from tiny images - Circuitnet: An open-source dataset for machine learning in vlsi cad applications with improved domain-specific evaluation metric and learning strategies - Circuitnet 2.0: An advanced dataset for promoting machine learning innovations in realistic chip design environment - OpenLS-DGF: An adaptive open-source dataset generation framework for machine learning tasks in logic synthesis - Building openlane: a 130nm openroad-based tapeout-proven flow - Open circuit design - Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering - The epfl combinational benchmark suite - Exact benchmark circuits for logic synthesis - Opencores - Rt-level itc’99 benchmarks and first atpg results ### **AI for Circuit Analysis** - Graph representation learning: a survey - Drills: Deep reinforcement learning for logic synthesis - Openabc-d: A large-scale dataset for machine learning guided integrated circuit synthesis - Area-driven fpga logic synthesis using reinforcement learning - Semi-supervised classification with graph convolutional networks - Inductive representation learning on large graphs - Neural message passing for quantum chemistry - Deepgate2: Functionality-aware circuit representation learning - Gamora: Graph learning based symbolic reasoning for large-scale boolean networks - Directed acyclic graph neural networks - Graph attention networks - D-vae: A variational autoencoder for directed acyclic graphs - Functionality matters in netlist representation learning - Deepgate: learning neural representations of logic gates - Deepseq: Deep sequential circuit learning - Deepseq2: Enhanced sequential circuit learning with disentangled representations - Deepgate3: Towards scalable circuit representation learning - Converts: Contrastively learning structurally invariant netlist representations - Deep learning-based circuit recognition using sparse mapping and level-dependent decaying sum circuit representations - Circuit representation learning with masked gate modeling and verilog-AIG alignment - High-speed adder design space exploration via graph neural processes - Deepcell: Multiview representation learning for post-mapping netlists - Fgnn2: A powerful pretraining framework for learning the logic functionality of circuits - Deepsat: An eda-driven learning framework for sat - Versatile multi-stage graph neural network for circuit representation - Calculating signal controllability using neural networks: Improvements to testability analysis and test point insertion - Test point insertion with deep reinforcement learning - Graph learning-based arithmetic block identification - Graph neural network based netlist operator detection under circuit rewriting - Invited paper: Verilog-to-pyg - a framework for graph learning and augmentation on rtl designs - The vtr project: architecture and cad for fpgas from verilog to routing - Deepgate4: Efficient and effective representation learning for circuit design at scale - Less is more: Hop-wise graph attention for scalable and generalizable learning on circuits - Polargate: Breaking the functionality representation bottleneck of and-inverter graph neural network ### **AI for Logic Optimization** - FRAIGs: A unifying representation for logic synthesis and verification - Delay optimization using SOP balancing - Scalable logic synthesis using a simple circuit structure - Deep learning for logic optimization algorithms - How powerful are graph neural networks? - Lostin: Logic optimization via spatio-temporal information with hybrid graph models - The prediction of the quality of results in logic synthesis using transformer and graph neural networks - Multimodal deep learning for biomedical data fusion: a review - Mtlso: A multi-task learning approach for logic synthesis optimization - Logic synthesis optimization with predictive self-supervision via causal transformers - Developing synthesis flows without human knowledge - Decision making in synthesis cross technologies using lstms and transfer learning - GRANNITE: Graph neural network inference for transferable power estimation - Bulls-eye: Active few-shot learning guided logic synthesis - Lstp: A logic synthesis timing predictor - Congestionnet: Routing congestion prediction using deep graph neural networks - Ceconp: Exploring node centrality for early routing congestion prediction - Lsoracle: a logic synthesis framework driven by artificial intelligence: Invited paper - The map method for synthesis of combinational logic circuits - HeLO: A heterogeneous logic optimization framework by hierarchical clustering and graph learning - Boils: Bayesian optimisation for logic synthesis - Batch sequential black-box optimization with embedding alignment cells for logic synthesis - Alphasyn: Logic synthesis optimization with efficient monte carlo tree search - Retrieval-guided reinforcement learning for boolean circuit minimization - Automatic multi-parameter tuning for logic synthesis with reinforcement learning - Exploring logic optimizations with reinforcement learning and graph convolutional network - Logic synthesis optimization sequence tuning using rl-based lstm and graph isomorphism network - Easyso: Exploration-enhanced reinforcement learning for logic synthesis sequence optimization and a comprehensive rl environment - Flowtune: End-to-end automatic logic optimization exploration via domain-specific multiarmed bandit - An efficient reinforcement learning based framework for exploring logic synthesis - AISyn: AI-driven reinforcement learning-based logic synthesis framework - Adaptive reconvergence-driven aig rewriting via strategy learning - A circuit domain generalization framework for efficient logic synthesis in chip design - Slap: A supervised learning approach for priority cuts technology mapping - Rl-mul: Multiplier design optimization with deep reinforcement learning - Prefixrl: Optimization of parallel prefix circuits using deep reinforcement learning - Circuitvae: Efficient and scalable latent circuit optimization ### **AI for Technology Mapping** - A new retiming-based technology mapping algorithm for LUT-based FPGAs - A survey of boolean matching techniques for library binding - Flowmap: an optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs - Simultaneous depth and area minimization in lut-based fpga mapping - Combinational and sequential mapping with priority cuts - Slap: A supervised learning approach for priority cuts technology mapping - Attention-based mechanism for technology mapping optimization - Machine-learning based delay prediction for fpga technology mapping - Lightgbm: A highly efficient gradient boosting decision tree - Aimap: Learning to improve technology mapping for asics via delay prediction ### **AI for Exact Synthesis** - Multiple-valued minimization for PLA optimization - Practical sat-a tutorial on applied satisfiability solving - Logic synthesis meets machine learning: Trading exactness for generalization - International workshop on logic and synthesis contest - A review of machine learning in logic synthesis - On PAC learning algorithms for rich boolean function classes - Statistical queries and statistical algorithms: Foundations and applications - Towards next-generation logic synthesis: A scalable neural circuit generation framework - DARTS: Differentiable architecture search - Deep differentiable logic gate networks - Categorical reparameterization with gumbel-softmax - Seadag: Semi-autoregressive diffusion for conditional directed acyclic graph generation - Neural combinatorial logic circuit synthesis from input-output examples - Optimizing computer systems with more generalized ai tools - Architect of the bits world: Masked autoregressive modeling for circuit generation guided by truth table - Shortcircuit: Alphazero-driven generative circuit design - Circuit transformer: A transformer that preserves logical equivalence - Logic synthesis with generative deep neural networks - Boolformer: Symbolic regression of logic functions with transformers - Can symbolic regression of boolean functions boost logic synthesis? - Sampling-based approximate logic synthesis: An explainable machine learning approach - LayerDAG: A layerwise autoregressive diffusion model for directed acyclic graph generation - Beswac: Boosting exact synthesis via wiser sat solver call ## **AI for Physical Design** ### **AI for Physical Design Dataset and Library** ### **AI for Placement** ### **AI for Routing** ### **AI for Timing and Power** ### **AI for Routability and DRC** ## **AI for Verification** - Machine learning methods in solving the boolean satisfiability problem - Machine learning for automated theorem proving: Learning to solve sat and qsat - Learning a sat solver from single-bit supervision - Predicting propositional satisfiability via end-to-end learning - Predicting propositional satisfiability based on graph attention networks - Satformer: Transformer-based unsat core learning - Learning to solve circuit-sat: An unsupervised differentiable approach - Sat-gatv2: A dynamic attention-based graph neural network for solving boolean satisfiability problem - Goal-aware neural sat solver - Guiding high-performance sat solvers with unsat-core predictions - Can q-learning with graph networks learn a generalizable branching heuristic for a sat solver? - Learning local search heuristics for boolean satisfiability - Neuroback: Improving cdcl sat solving using graph neural networks - Learning cubing heuristics for sat from drat proofs - Graph neural reasoning may fail in certifying boolean unsatisfiability - Nlocalsat: Boosting local search with solution prediction ## **AI for Test Synthesis** - On using machine learning for logic bist - A survey and recent advances: Machine intelligence in electronic testing - Test point insertion using artificial neural networks - Applying neural networks to delay fault testing: Test point insertion and random circuit training - High performance graph convolutional networks with applications in testability analysis - Applying artificial neural networks to logic built-in self-test: Improving test point insertion - Test point selection using deep graph convolutional networks and advantage actor critic (a2c) reinforcement learning - Toward zero backtracks in test pattern search algorithms with machine learning - Machine intelligence for efficient test pattern generation - Training neural network for machine intelligence in automatic test pattern generator - A graph autoencoder approach for fault prediction in test pattern generation ## **AI for Security** - Sail: Machine learning guided structural analysis attack on hardware obfuscation - An oracle-less machine-learning attack against lookup-table-based logic locking - Untangle: Unlocking routing and logic obfuscation using graph neural networks-based link prediction - Galu: A genetic algorithm framework for logic unlocking - Omla: An oracle-less machine learning-based attack on logic locking - Muxlink: Circumventing learning-resilient mux-locking using graph neural network-based link prediction - INSIGHT: Attacking Industry-Adopted learning resilient logic locking techniques using explainable graph neural network - Gnnreveal: A novel graph neural network-based attack method for ic logic gate de-camouflaging - Gnn-re: Graph neural networks for reverse engineering of gate-level netlists - Flip-lock: A flip-flop-based logic locking technique for thwarting ml-based and algorithmic structural attacks - Gnn4ip: Graph neural network for hardware intellectual property piracy detection ## **AI for Physical Simulation** ``` This is an open list. We welcome everyone to update it together. ```