diff --git a/Fix-the-processing-flow-of-RISC-V-iSCSI-checksum.patch b/Fix-the-processing-flow-of-RISC-V-iSCSI-checksum.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f17b202415cf42169579a6fe1fcb680603f5278a
--- /dev/null
+++ b/Fix-the-processing-flow-of-RISC-V-iSCSI-checksum.patch
@@ -0,0 +1,73 @@
+From 8d4e4e568db248ef68d4a138e1458ceca5adc1ea Mon Sep 17 00:00:00 2001
+From: dongji <dong.ji1@zte.com.cn>
+Date: Tue, 9 Dec 2025 09:00:30 +0800
+Subject: [PATCH] Fix the processing flow of the iSCSI checksum
+
+ Testing
+ The verification method involves
+ running autogen.sh and configure to generate the Makefile, followed by
+ executing the make checks command. The verification results below were
+ obtained on a RISC-V64 OpenEuler 24.03 LTS-SP3 virtual machine on QEMU
+ 9.0.1
+
+ All tests successful.
+ make --no-print-directory check-TESTS
+ PASS: raid/pq_gen_test
+ PASS: crc/crc16_t10dif_test
+ PASS: crc/crc16_t10dif_copy_test
+ PASS: raid/xor_gen_test
+ PASS: crc/crc64_funcs_test
+ PASS: crc/crc32_funcs_test
+ PASS: igzip/igzip_wrapper_hdr_test
+ PASS: igzip/checksum32_funcs_test
+ PASS: erasure_code/gf_inverse_test
+ PASS: erasure_code/gf_vect_mul_test
+ PASS: raid/xor_check_test
+ PASS: raid/pq_check_test
+ PASS: igzip/igzip_rand_test
+ PASS: mem/mem_zero_detect_test
+ PASS: erasure_code/erasure_code_test
+ PASS: erasure_code/erasure_code_update_test
+ ============================================================================
+ Testsuite summary for libisal 2.30.0
+ ============================================================================
+ # TOTAL: 16
+ # PASS:  16
+ # SKIP:  0
+ # XFAIL: 0
+ # FAIL:  0
+ # XPASS: 0
+ # ERROR: 0
+ ============================================================================
+
+Signed-off-by: liuqingtao <liu.qingtao2@zte.com.cn>
+---
+ crc/riscv64/crc32_iscsi_refl_vclmul.S | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/crc/riscv64/crc32_iscsi_refl_vclmul.S b/crc/riscv64/crc32_iscsi_refl_vclmul.S
+index 1534238..969bb6a 100644
+--- a/crc/riscv64/crc32_iscsi_refl_vclmul.S
++++ b/crc/riscv64/crc32_iscsi_refl_vclmul.S
+@@ -41,9 +41,7 @@ crc32_iscsi_refl_vclmul:
+     sext.w a2, a1
+     mv a1, a0
+     mv a0, a7
+-    li t5, 0xffffffff
+     xori a0, a0, -1
+-    and a0, a0, t5
+     addi sp, sp, -8
+     sd ra, (sp)
+ 1:
+@@ -52,6 +50,5 @@ crc32_iscsi_refl_vclmul:
+     ld ra, (sp)
+     addi sp, sp, 8
+     xori a0, a0, -1
+-    and a0, a0, t5
+     ret
+-#endif
+\ No newline at end of file
++#endif
+-- 
+2.43.0
+
diff --git a/isa-l.spec b/isa-l.spec
index cdf176083f1a3609c399940d73c26cd4072176ea..2deb9a3c9919f7761de3702e36caa355718d0354 100644
--- a/isa-l.spec
+++ b/isa-l.spec
@@ -2,7 +2,7 @@
 %define isal_devname libisa-l-devel
 Name:                isa-l
 Version:             2.30.0
-Release:             4
+Release:             5
 Summary:             Intelligent Storage Acceleration Library
 License:             BSD-3-Clause
 URL:                 https://github.com/intel/isa-l
@@ -10,6 +10,7 @@ Source0:             https://github.com/intel/isa-l/archive/refs/tags/v%{version
 
 Patch1:              Feature-Add-Basic-RISC-V-And-CRC-Vector-support.patch
 Patch2:              Feature-Optimize-CRC-calculation-for-the-RISC-V.patch
+Patch3:              Fix-the-processing-flow-of-RISC-V-iSCSI-checksum.patch
 
 BuildRequires:       yasm  gcc
 BuildRequires:       autoconf automake libtool
@@ -71,6 +72,9 @@ find %{?buildroot} -name *.la -print0 | xargs -r0 rm -f
 %{_libdir}/pkgconfig/libisal.pc
 
 %changelog
+* Tue Dec 09 2025 liuqingtao <liu.qingtao2@zte.com.cn> - 2.30.0-5
+- Fix the processing flow of RISC-V iSCSI checksum
+
 * Tue Sep 09 2025 liuqingtao <liu.qingtao2@zte.com.cn> - 2.30.0-4
 - Optimize CRC calculation for the RISC-V