# verilogRTL

**Repository Path**: wwkkww1983/verilog-rtl

## Basic Information

- **Project Name**: verilogRTL
- **Description**: verilogRTL实践课程
- **Primary Language**: Verilog
- **License**: Apache-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2021-09-15
- **Last Updated**: 2022-06-07

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

- 文件夹内容提示

# verilogRTL

[verilogRTL实践课程](https://www.bilibili.com/video/BV1wJ41137J5)

# VLSI_LabCDROM

- Verilog数字VLSI设计教程_[李林 编著]

# ModelSim

[ModelSim(第2版)电子系统分析及仿真 源程序](https://blog.csdn.net/haojie_duan/article/details/119136420)